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ds092 (v3.0) november 30, 2005 www.xilinx.com 1 product specification ? 2005 xilinx, inc. all rights reserved. all xilinx trademarks, registered trademarks, patents, and disclaimers are as listed a t http://www.xilinx.com/legal.htm . all other trademarks and registered trademarks are the property of their respective owners. all specifications are subject to c hange without notice. note: this product is being discontinued. you cannot order this part after april 24, 2006. xilinx recommends replacing the xc2c64 device with the xc2c64a device in all designs as soon as possible. the xc2c64a device is pin-to-pin compatible with the xc2c64 device. see xcn05017 for details regarding the discontinuation of the xc2c64 device. features ? optimized for 1.8v systems - as fast as 4.6 ns pin-to-pin logic delays - as low as 15 a quiescent current ? industries best 0.18 micron cmos cpld - optimized architecture for effective logic synthesis - multi-voltage i/o operation ? 1.5v to 3.3v ? available in multiple package options - 44-pin plcc with 33 user i/o - 44-pin vqfp with 33 user i/o - 56-ball cp bga with 45 user i/o - 100-pin vqfp with 64 user i/o ? advanced system features - fastest in system programming 1.8v isp using ieee 1532 (jtag) interface - ieee1149.1 jtag boundary scan test - optional schmitt-trigger input (per pin) - realdigital? 100% cmos product term generation - flexible clocking modes optional dualedge triggered registers - global signal options with macrocell control multiple global clocks with phase selection per macrocell multiple global output enables global set/reset - efficient control term clocks, output enables and set/resets for each macrocell and shared across function blocks - advanced design security - open-drain output option for wired-or and led drive - optional configurable grounds on unused i/os - optional bus-hold, 3-state or weak pull-up on selected i/o pins - mixed i/o voltages compatible with 1.5v, 1.8v, 2.5v, and 3.3v logic levels - pla architecture superior pinout retention 100% product term routability across function block - hot pluggable refer to the coolrunner?-ii family data sheet for architec- ture description. description the coolrunner-ii 64-macrocell device is designed for both high performance and low power applications. this lends power savings to high-end communication equipment and high speed to battery operated devices. due to the low power stand-by and dynamic operation, overall system reli- ability is improved this device consists of four function blocks inter-con- nected by a low power advanced interconnect matrix (aim). the aim feeds 40 true and complement inputs to each function block. the function blocks consist of a 40 by 56 p-term pla and 16 macrocells which contain numerous configuration bits that allow for combinational or registered modes of operation. additionally, these registers can be globally reset or preset and configured as a d or t flip-flop or as a d latch. there are also multiple clock signals, both global and local product term types, configured on a per macrocell basis. output pin configurations include slew rate limit, bus hold, pull-up, open drain and programmable grounds. a schmitt trigger input is available on a per input pin basis. in addition to stor- ing macrocell output states, the macrocell registers may be configured as "direct input" registers to store signals directly from input pins. clocking is available on a global or function block basis. three global clocks are available for all function blocks as a synchronous clock source. macrocell registers can be individually configured to power up to the zero or one state. a global set/reset control line is also available to asynchro- nously set or reset selected registers during operation. additional local clock, synchronous clock-enable, asynchro- nous set/reset and output enable signals can be formed using product terms on a per-macrocell or per-function block basis. a dualedge flip-flop feature is also available on a per mac- rocell basis. this feature allows high performance synchro- nous operation based on lower frequency clocking to help reduce the total power consumption of the device. the coolrunner-ii 64-macrocell cpld is i/o compatible with standard lvttl and lvcmos18, lvcmos25, and 0 xc2c64 coolrunner-ii cpld ds092 (v3.0) november 30, 2005 00 product specification r
xc2c64 coolrunner-ii cpld 2 www.xilinx.com ds092 (v3.0) november 30, 2005 product specification r lvcmos33 (see ta b le 1 ). this device is also lvcomos15 compatible with the use of schmitt-trigger inputs. realdigital design technology xilinx coolrunner-ii cplds are fabricated on a 0.18 micron process technology which is derived from leading edge fpga product development. coolrunner-ii cplds employ realdigital, a design technique that makes use of cmos technology in both the fabrication and design methodology. realdigital design technology employs a cascade of cmos gates to implement sum of products instead of traditional sense amplifier methodology. due to this technology, xilinx coolrunner-ii cplds achieve both high performance and low power operation. supported i/o standards the coolrunner-ii 64 macrocell features both lvcmos and lvttl i/o implementations. see ta b l e 1 for i/o stan- dard voltages. the lvttl i/o standard is a general purpose eia/jedec standard for 3.3v applications that use an lvttl input buffer and push-pull output buffer. the lvcmos standard is used in 3.3v, 2.5v, 1.8v applications. coolrunner-ii cplds are also 1.5v i/o compatible with the use of schmitt-trigger inputs. table 1: i/o standards for xc2c64 iostandard attribute output v ccio input v ccio input v ref board termination voltage v t lvttl 3.3 3.3 n/a n/a lvcmos33 3.3 3.3 n/a n/a lvcmos25 2.5 2.5 n/a n/a lvcmos18 1.8 1.8 n/a n/a lvcmos15 (1) 1.5 1.5 n/a n/a (1) requires schmitt-trigger inputs. figure 1: i cc vs frequency table 2: i cc vs frequency (lvcmos 1.8v t a = 25c) (1) frequency (mhz) 0 25 50 75 100 150 175 200 225 240 typical i cc (ma) 0.015 1.8 3.7 5.5 7.48 11.0 12.7 14.6 15.3 17.77 notes: 1. 16-bit up/down, resetable binary counter (one counter per function block). frequency (mhz) ds092_01_09230 2 i cc (ma) 0 0 10 5 15 20 250 200 150 100 50
xc2c64 coolrunner-ii cpld ds092 (v3.0) november 30, 2005 www.xilinx.com 3 product specification r recommended operating conditions dc electrical characteristics (over recommended operating conditions) absolute maximum ratings symbol description value units v cc supply voltage relative to ground ?0.5 to 2.0 v v ccio supply voltage for output drivers ?0.5 to 4.0 v v jtag (2) jtag input voltage limits ?0.5 to 4.0 v v aux jtag input supply voltage ?0.5 to 4.0 v v in (1) input voltage relative to ground ?0.5 to 4.0 v v ts (1) voltage applied to 3-state output ?0.5 to 4.0 v v stg (3) storage temperature (ambient) ?65 to +150 c t j junction temperature +150 c notes: 1. maximum dc undershoot below gnd must be limited to either 0.5v or 10 ma, whichever is easiest to achieve. during transitions, the device pins may undershoot to ?2.0v or overshoot to +4.5v, provided this over or undershoot lasts less than 10 ns and with t he forcing current being limited to 200 ma. 2. valid over commercial temperature range. 3. for soldering guidelines and thermal considerations, see the device packaging information on the xilinx website. for pb free packages, see xapp427 . symbol parameter min max units v cc supply voltage for internal logic and input buffers commercial t a = 0c to +70c 1.7 1.9 v industrial t a = ?40c to +85c 1.7 1.9 v v ccio supply voltage for output drivers @ 3.3v operation 3.0 3.6 v supply voltage for output drivers @ 2.5v operation 2.3 2.7 v supply voltage for output drivers @ 1.8v operation 1.7 1.9 v supply voltage for output drivers @ 1.5v operation 1.4 1.6 v v aux jtag programming pins 1.7 3.6 v symbol parameter test conditions typical max. units i ccsb standby current commercial v cc = 1.9v, v ccio = 3.6v 100 a i ccsb standby current industrial v cc = 1.9v, v ccio = 3.6v 165 a i cc (1) dynamic current f = 1 mhz 500 a f = 50 mhz 5 ma c jtag jtag input capacitance f = 1 mhz 10 pf c clk global clock input capacitance f = 1 mhz 12 pf c io i/o capacitance f = 1 mhz 10 pf i il (2) input leakage current v in = 0v or v ccio to 3.9v +/-1 a i ih (2) i/o high-z leakage v in = 0v or v ccio to 3.9v +/-1 a notes: 1. 16-bit up/down, resetable binary counter (one counter per function block) tested at v cc =v ccio = 1.9v. 2. see quality and reliability section of the coolrunner-ii family data sheet.
xc2c64 coolrunner-ii cpld 4 www.xilinx.com ds092 (v3.0) november 30, 2005 product specification r lvcmos 3.3v and lvttl 3.3v dc voltage specifications lvcmos 2.5v dc voltage specifications symbol parameter test conditions min. max. units v ccio input source voltage 3.0 3.6 v v ih high level input voltage 2 3.9 v v il low level input voltage ?0.3 0.8 v v oh high level output voltage i oh = ?8 ma, v ccio = 3v v ccio ? 0.4v - v i oh = ?0.1 ma, v ccio = 3v v ccio ? 0.2v - v v ol low level output voltage i ol = 8 ma, v ccio = 3v - 0.4 v i ol = 0.1 ma, v ccio = 3v - 0.2 v symbol parameter test conditions min. max. units v ccio input source voltage 2.3 2.7 v v ih high level input voltage 1.7 3.9 v v il low level input voltage ?0.3 0.7 v v oh high level output voltage i oh = ?8 ma, v ccio = 2.3v v ccio ? 0.4v - v i oh = ?0.1 ma, v ccio = 2.3v v ccio ? 0.2v - v v ol low level output voltage i ol = 8 ma, v ccio = 2.3v - 0.4 v i ol = 0.1 ma, v ccio = 2.3v - 0.2 v
xc2c64 coolrunner-ii cpld ds092 (v3.0) november 30, 2005 www.xilinx.com 5 product specification r lvcmos 1.8v dc voltage specifications lvcmos 1.5v dc voltage specifications (1) schmitt trigger input dc voltage specifications ac electrical characteristics over recommended operating conditions symbol parameter test conditions min. max. units v ccio input source voltage 1.7 1.9 v v ih high level input voltage 0.65 x v ccio 3.9 v v il low level input voltage ?0.3 0.35 x v ccio v v oh high level output voltage i oh = ?8 ma, v ccio = 1.7v v ccio ? 0.45 - v i oh = ?0.1 ma, v ccio = 1.7v v ccio ? 0.2 - v v ol low level output voltage i ol = 8 ma, v ccio = 1.7v - 0.45 v i ol = 0.1 ma, v ccio = 1.7v - 0.2 v symbol parameter test conditions min. max. units v ccio input source voltage 1.4 1.6 v v t+ input hysteresis threshold voltage 0.5 x v ccio 0.8 x v ccio v v t- 0.2 x v ccio 0.5 x v ccio v v oh high level output voltage i oh = ?4 ma, v ccio = 1.4v v ccio ? 0.45 - v i oh = ?0.1 ma, v ccio = 1.4v v ccio ? 0.2 - v v ol low level output voltage i ol = 8 ma, v ccio = 1.4v - 0.4 v i ol = 0.1 ma, v ccio = 1.4v - 0.2 v notes: 1. hysteresis used on 1.5v inputs. symbol parameter test conditions min. max. units v ccio input source voltage 1.4 3.9 v v t+ input hysteresis threshold voltage 0.5 x v ccio 0.8 x v ccio v v t- 0.2 x v ccio 0.5 x v ccio v symbol parameter -5 -7 units min. max. min. max. t pd1 propagation delay single p-term - 4.6 - 6.7 ns t pd2 propagation delay or array - 5.0 - 7.5 ns t sud direct input register clock setup time 2.4 - 3.3 - ns t su1 setup time (single p-term) 2.0 - 2.5 - ns t su2 setup time (or array) 2.4 - 3.3 - ns t hd direct input register hold time 0 - 0 - ns t h p-term hold time 0 - 0 - ns
xc2c64 coolrunner-ii cpld 6 www.xilinx.com ds092 (v3.0) november 30, 2005 product specification r t co clock to output - 3.9 - 6.0 ns f toggle (1) internal toggle rate (1) - 333 - 200 mhz f system1 (2) maximum system frequency (2) - 263 - 159 mhz f system2 (2) maximum system frequency (2) - 238 - 141 mhz f ext1 (3) maximum external frequency (3) -169-118mhz f ext2 (3) maximum external frequency (3) - 159 - 108 mhz t psud direct input register p-term clock setup time 0.9 - 1.7 - ns t psu1 p-term clock setup time (single p-term) 0.5 - 0.9 - ns t psu2 p-term clock setup time (or array) 0.9 - 1.7 - ns t phd direct input register p-term clock hold time 1.1 - 0.9 - ns t ph p-term clock hold 1.5 - 1.7 - ns t pco p-term clock to output - 6.0 - 8.4 ns t oe /t od global oe to output enable/disable - 8.0 - 10.0 ns t poe /t pod p-term oe to output enable/disable - 9.0 - 11.0 ns t moe /t mod macrocell driven oe to output enable/disable - 9.0 - 11.0 ns t pao p-term set/reset to output valid - 7.3 - 9.7 ns t ao global set/reset to output valid - 6.0 - 8.3 ns t suec register clock enable setup time 3.0 - 3.7 - ns t hec register clock enable hold time 0 - 0 - ns t cw global clock pulse width high or low 1.5 - 2.5 - ns t pcw p-term pulse width high or low 5.0 - 7.5 - ns t aprpw asynchronous preset/reset pulse width (high or low) 5.0 - 7.5 - ns t config (4) configuration time - 50.0 - 50.0 s notes: 1. f toggle (1/2*t cw ) is the maximum frequency of a dual edge triggered t flip-flop with output enabled. 2. f system (1/t cycle ) is the internal operating frequency for a device fully populated with 16-bit up/down, resetable binary counter (one counter per function block). 3. f ext (1/t su1 +t co ) is the maximum external frequency. 4. typical configuration current during t config is 2.3 ma. symbol parameter -5 -7 units min. max. min. max.
xc2c64 coolrunner-ii cpld ds092 (v3.0) november 30, 2005 www.xilinx.com 7 product specification r internal timing parameters symbol parameter (1) -5 -7 units min. max. min. max. buffer delays t in input buffer delay - 1.7 - 2.4 ns t din direct data register input delay - 2.6 - 4.0 ns t gck global clock buffer delay - 1.6 - 2.5 ns t gsr global set/reset buffer delay - 2.4 - 3.5 ns t gts global 3-state buffer delay - 2.7 - 3.9 ns t out output buffer delay - 1.9 - 2.8 ns t en output buffer enable/disable delay - 5.3 - 6.1 ns p-term delays t ct control term delay - 2.0 - 2.5 ns t logi1 single p-term delay adder - 0.5 - 0.8 ns t logi2 multiple p-term delay adder - 0.4 - 0.8 ns macrocell delay t pdi input to output valid - 0.5 - 0.7 ns t sui setup before clock 1.4 - 1.8 - ns t hi hold after clock 0.0 - 0.0 - ns t ecsu enable clock setup time 0.9 - 1.3 - ns t echo enable clock hold time 0 - 0 - ns t coi clock to output valid - 0.4 - 0.7 ns t aoi set/reset to output valid - 1.7 - 2.0 ns t cdbl clock doubler delay - 0 - 0 ns feedback delays t f feedback delay - 1.5 - 2.0 ns t oem macrocell to global oe delay - 1.7 - 1.7 ns i/o standard time adder delays 1.5v cmos t hys15 hysteresis input adder - 4.0 - 6.0 ns t out15 output adder - 0.9 - 1.5 ns t slew15 output slew rate adder - 4.0 - 6.0 ns i/o standard time adder delays 1.8v cmos t hys18 hysteresis input adder - 3.0 - 4.0 ns t out18 output adder - 0 - 0 ns t slew output slew rate adder - 3.5 - 5.0 ns
xc2c64 coolrunner-ii cpld 8 www.xilinx.com ds092 (v3.0) november 30, 2005 product specification r i/o standard time adder delays 2.5v cmos t in25 standard input adder - 0.5 - 1.0 ns t hys25 hysteresis input adder - 2.5 - 3.0 ns t out25 output adder - 4.8 - 6.0 ns t slew25 output slew rate adder - 2.5 - 4.0 ns i/o standard time adder delays 3.3v cmos/ttl t in33 standard input adder - 0.5 - 1.0 ns t hys33 hysteresis input adder - 2.0 - 3.0 ns t out33 output adder - 7.0 - 10.0 ns t slew33 output slew rate adder - 2.5 - 4.0 ns notes: 1. 1.5 ns input pin signal rise/fall. internal timing parameters (continued) symbol parameter (1) -5 -7 units min. max. min. max.
xc2c64 coolrunner-ii cpld ds092 (v3.0) november 30, 2005 www.xilinx.com 9 product specification r switching characteristics ac test circuit typical i/o output curves figure 4: typical i/o output curves figure 2: derating curve for t pd figure 3: ac load circuit number of outputs switching 12 4 8 1 6 3.0 4.0 5.0 v cc = v ccio = 1.8v, t = 25 o c t pd2 (ns) 5.5 4.5 3.5 ds092_02_09230 2 r 1 v cc c l r 2 device under test output type lvttl33 lvcmos33 lvcmos25 lvcmos18 lvcmos15 r 1 268 ? 275 ? 188 ? 112.5 ? 150 ? r 2 235 ? 275 ? 188 ? 112.5 ? 150 ? c l 35 pf 35 pf 35 pf 35 pf 35 pf ds092_03_09230 2 test point notes: 1. c l includes test fixtures and probe capacitance. 2. 1.5 nsec maximum rise/fall times on inputs. ds092_07_092302 0 0 80 20 100 40 60 120 3.0 2.5 2.0 1.5 1.0 0.5 3 .5 v o output volts i o output current (ma) 3.3v 2.5v 1.8v 1.5v
xc2c64 coolrunner-ii cpld 10 www.xilinx.com ds092 (v3.0) november 30, 2005 product specification r pin descriptions function block macrocell pc44 vq44 cp56 vq100 1 1 44 38 f1 13 1 2 43 37 e3 12 1 3 42 36 e1 11 14---10 15---9 16---8 17---7 18---6 1(gts1) 9 40 34 d1 4 1(gts0) 10 39 33 c1 3 1(gts3) 11 3832a3 2 1(gts2) 12 3731a2 1 1(gsr) 13 36 30 b1 99 114--a197 115--c394 116---92 21139g114 22240f315 23---16 24---17 25341h118 26442g319 2(gck0) 7 5 43 j1 22 2(gck1) 8 6 44 k1 23 29--k424 2(gck2) 10 7 1 k2 27 211---28 21282k329 21393h330 214--k532 215---33 216---34
xc2c64 coolrunner-ii cpld ds092 (v3.0) november 30, 2005 www.xilinx.com 11 product specification r 1. gts = global output enable, gsr = global set reset, gck = global clock. 3 1 35 29 c4 91 3 2 34 28 a4 90 3 3 33 27 c5 89 34--a781 35--c879 3 6 29 23 a8 78 37--a977 38---76 39--a574 3 10 28 22 a10 72 3 11 27 21 b10 71 3122620c1070 313--d868 3 14 2519e867 3152418d1064 316---61 41115k635 42126h536 43--k737 44---39 45--h740 46---41 47148h842 48---43 49---49 410--k850 4111812h1052 412---53 4 13 19 13 g10 55 4142014-56 4 15 22 16 f10 58 4 16 - - e10 60 pin descriptions (continued) function block macrocell pc44 vq44 cp56 vq100
xc2c64 coolrunner-ii cpld 12 www.xilinx.com ds092 (v3.0) november 30, 2005 product specification r xc2c64 global, jtag, power/ground and no connect pins ordering information pin type pc44 vq44 cp56 vq100 tck 17 11 k10 48 tdi 15 9 j10 45 tdo 30 24 a6 83 tms 16 10 k9 47 v aux (jtag supply voltage) 41 35 d3 5 power internal (v cc ) power external i/o (v ccio ) 21 15 g8 26,57 13, 32 7, 26 h6, c6 38, 51, 88, 98 ground 10, 23, 31 4,17,25 h4, f8, c7 21, 31, 62, 69, 84,100 no connects 20, 25, 44, 46, 54, 59, 63, 65, 66, 73, 75, 80, 82, 85, 86, 87, 93, 95, 96 total user i/o 33 33 45 64 device ordering no. and part marking no. pin/ball spacing ja (c/watt) jc (c/watt) package type package body dimensions i/o comm. (c) ind. (i) (1) xc2c64-5pc44c 1.27mm 53.1 28.7 plastic leaded chip carrier 16.5mm x 16.5mm 33 c xc2c64-7pc44c 1.27mm 53.1 28.7 plastic leaded chip carrier 16.5mm x 16.5mm 33 c xc2c64-5vq44c 0.8mm 46.6 8.2 very thin quad flat pack 10mm x 10mm 33 c xc2c64-7vq44c 0.8mm 46.6 8.2 very thin quad flat pack 10mm x 10mm 33 c xc2c64-5cp56c 0.5mm 65.0 15.0 chip scale package 6mm x 6mm 45 c xc2c64-7cp56c 0.5mm 65.0 15.0 chip scale package 6mm x 6mm 45 c xc2c64-5vq100c 0.5mm 53.2 14.6 very thin quad flat pack 14mm x 14mm 64 c xc2c64-7vq100c 0.5mm 53.2 14.6 very thin quad flat pack 14mm x 14mm 64 c xc2c64-7pc44i 1.27mm 53.1 28.7 plastic leaded chip carrier 16.5mm x 16.5mm 33 i xc2c64-7vq44i 0.8mm 46.6 8.2 very thin quad flat pack 10mm x 10mm 33 i xc2c64-7cp56i 0.5mm 65.0 15.0 chip scale package 6mm x 6mm 45 i xc2c64-7vq100i 0.5mm 53.2 14.6 very thin quad flat pack 14mm x 14mm 64 i notes: 1. c = commercial (t a = 0c to +70c); i = industrial (t a = ?40c to +85c). standard example: xc2c128 device speed grade package type number of pins temperature range -4 tq c 144 pb- free example: xc2c128 tq g 144 c device speed grade package type pb -free number of pins -4 temperature range
xc2c64 coolrunner-ii cpld ds092 (v3.0) november 30, 2005 www.xilinx.com 13 product specification r device part marking figure 5: sample package with part marking note: due to the small size of chip scale packages, the complete ordering part number cannot be included on the package marking. part marking on chip scale packages by line are: 1. x (xilinx logo) truncated device part number 2. not related to device part number 3. not related to device part number 4. device code, speed, operating temperature, three digits not related to device part number. device codes: c3 = cp56, c4 = cpg56. xc2cxxx tq144 7c device type package speed operating range this line not related to device part number r part marking for non-chip scale package
xc2c64 coolrunner-ii cpld 14 www.xilinx.com ds092 (v3.0) november 30, 2005 product specification r package pinout diagrams figure 6: vq44 package figure 7: pc44 package vq44 top view i/o (1) i/o (1) i/o (1) i/o (3) i/o i/o i/o v ccio gnd tdo i/o i/o (2 ) i/o (2 ) i/o i/o i/o i/o i/o i/o i/o v au x i/o (1 ) i/o i/o i/o v cc i/o gnd i/o i/o i/o i/o i/o i/ o (2) i/o i/o g nd i/o i/o v c cio i/o tdi t ms t ck 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 33 32 31 30 29 28 27 26 25 24 23 44 43 42 41 40 39 38 37 36 35 34 (1) - global output enab le (2) - global clock (3) - global set/reset pc44 top view i/o (1) i/o (1) i/o (1) i/o (3) i/o i/o i/o v ccio gnd tdo i/o i/o (2 ) i/o (2 ) i/o i/o i/o i/o i/o i/o i/o v au x i/o (1 ) i/o i/o i/o v cc i/o gnd i/o i/o i/o i/o i/o i/o (2) i/o i/o gnd i/o i/o v ccio i/o tdi tms tck 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 39 38 37 36 35 34 33 32 31 30 29 6 5 4 3 2 1 44 43 42 41 40 (1) - global output enab le (2) - global clock (3) - global set/reset figure 8: cp56 package cp56 bottom view i/o (2) i/o (2) i/o i/o i/o i/o i/o i/o tms tck i/o (2) tdi i/o i/o gnd i/o v ccio i/o i/o i/o i/o i/o v cc i/o i/o i/o gnd i/o i/o i/o i/o i/o i/o (1) v aux i/o i/o i/o (1) i/o i/o i/o v ccio gnd i/o i/o i/o (3) i/o i/o i/o (1) i/o (1) i/o i/o tdo i/o i/o i/o i/o k j h g f e d c b a 1 2 3 4 5 6 7 8 9 1 0 (1) - global output enable (2) - global clock
xc2c64 coolrunner-ii cpld ds092 (v3.0) november 30, 2005 www.xilinx.com 15 product specification r additional information coolrunner-ii data sheets and application notes online store package drawings figure 12: vq100 package vq100 top view gnd i/o (3 ) v cci o i/o nc nc i/o nc i/o i/o i/o i/o v cci o nc nc nc gnd tdo nc i/o nc i/o i/o i/o i/o v cc i/o (2) i/o i/o i/o gnd i/o i/o i/o i/o i/o i/o v ccio i/o i/o i/o i/o i/o nc tdi nc tms tck i/o i/o nc i/o nc i/o i/o i/o gnd i/o i/o nc nc i/o nc gnd i/o i/o nc i/o vcc i/o i/o nc i/o i/o v cc io i /o (1) i /o (1) i /o (1) i /o (1) v aux i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o nc g nd i /o (2) i /o (2) i/o nc 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 (1) - global output enable (2) - global clock (3) - global set/reset
xc2c64 coolrunner-ii cpld 16 www.xilinx.com ds092 (v3.0) november 30, 2005 product specification r revision history the following table shows the revision history for this document. date version revision 01/03/02 1.0 initial xilinx release. 03/04/02 1.1 removed a4 from the fb1, mc16, and cp56 in the pinout tables. updated v oh and v ol for lvcmos 2.5v, lvcmos 1.8v, and 1.5v dc voltage specifications. 04/09/02 1.2 removed fast industrial speed grade. updated 1.5 dc voltage, v oh parameter from i oh = ?0.8 ma to ?0.4 ma. 9/24/02 1.3 update ac characteristics and minor edits 9/27/02 1.4 changed ac characteristic t h2 to t h , packaging: changed vq100 dimensions from 12mm x 12mm to 14mm x 14mm. 01/26/04 1.5 added device part marking information; tsol update; added links. 7/1/04 1.6 changed tfin to tdin. added note recommending use of new xc2c64a device. removed advance specification of -4 speed grade. 10/01/04 1.7 add asynchronous preset/reset pulse width specification to ac electrical characteristics. 10/07/04 1.8 deleted note, page 1. 11/08/04 1.9 note added to recommend xc2c64a for new designs. 01/30/05 2.0 addition of i ccsb max for industrial grade. 03/07/05 2.1 modifications to iostandard table. 11/30/05 3.0 notice of obsolescence.

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